Analysis of the effect of finite d.c. blocking capacitance and finite d.c. feed inductance on the performance of inverse Class-E amplifiersMURY, T; FUSCO, V. F.IEE proceedings. Circuits, devices and systems. 2006, Vol 153, Num 2, pp 129-135, issn 1350-2409, 7 p.Article

High-order DDCC-based general mixed-mode universal filterCHANG, C.-M; LEE, C.-N; HOU, C.-L et al.IEE proceedings. Circuits, devices and systems. 2006, Vol 153, Num 5, pp 511-516, issn 1350-2409, 6 p.Article

Signed higher-radix full-adder algorithm and implementation with current-mode multi-valued logic circuitsTEMEL, T; MORGUL, A; AYDIN, N et al.IEE proceedings. Circuits, devices and systems. 2006, Vol 153, Num 5, pp 489-496, issn 1350-2409, 8 p.Article

Smoothing of the nonlinearity of some algebraic characteristics by means of 1-port structures composed of similar elementsGLUSKIN, E.IEE proceedings. Circuits, devices and systems. 2006, Vol 153, Num 2, pp 89-94, issn 1350-2409, 6 p.Article

Efficient and flexible architecture for AESLI, H.IEE proceedings. Circuits, devices and systems. 2006, Vol 153, Num 6, pp 533-538, issn 1350-2409, 6 p.Article

Hybrid multi-polarity arithmetic-Walsh transformFALKOWSKI, B. J; YAN, S.IEE proceedings. Circuits, devices and systems. 2006, Vol 153, Num 6, pp 591-598, issn 1350-2409, 8 p.Article

Effects of different buffer structures on the avalanche behaviour of high voltage diodes under high reverse current conditionsFELSL, H. P; HEINZE, B; LUTZ, J et al.IEE proceedings. Circuits, devices and systems. 2006, Vol 153, Num 1, pp 11-15, issn 1350-2409, 5 p.Conference Paper

Characteristics of a monolithic bidirectional switch (MBS) used in a diode functionCHMIELUS, S; SITTIG, R.IEE proceedings. Circuits, devices and systems. 2006, Vol 153, Num 1, pp 29-33, issn 1350-2409, 5 p.Conference Paper

Elucidation of the intrinsic loss arising from switch output capacitance C_oss in ultra-high-speed low-loss power convertersADACHI, K; TAKAO, K; OHASHI, H et al.IEE proceedings. Circuits, devices and systems. 2006, Vol 153, Num 1, pp 40-45, issn 1350-2409, 6 p.Conference Paper

Experimental validation of the 'Floating Islands' concept : 95 V breakdown voltage vertical FLIDiodeALVES, S; MORANCHO, F; REYNES, J.-M et al.IEE proceedings. Circuits, devices and systems. 2006, Vol 153, Num 1, pp 53-60, issn 1350-2409, 8 p.Conference Paper

Lateral power MOSFETs with drift trench electrodes and drain trench electrodes for a 42V automotive systemKANECHIKA, M; KODAMA, M; UESUGI, T et al.IEE proceedings. Circuits, devices and systems. 2006, Vol 153, Num 1, pp 61-66, issn 1350-2409, 6 p.Conference Paper

Weierstrass approach to blind source separation of multiple nonlinearly mixed signalsGAO, P; WOO, W. L; DLAY, S. S et al.IEE proceedings. Circuits, devices and systems. 2006, Vol 153, Num 4, pp 332-345, issn 1350-2409, 14 p.Conference Paper

0.7 V manchester carry look-ahead circuit using PD SOI CMOS asymmetrical dynamic threshold pass transistor techniques suitable for low-voltage CMOS VLSI systemsCHIANG, T. Y; KUO, J. B.IEE proceedings. Circuits, devices and systems. 2005, Vol 152, Num 2, pp 123-126, issn 1350-2409, 4 p.Article

10-bit switched-current digital-to-analogue converterTSAI, C.-C; LAI, C.-H; LEE, W.-T et al.IEE proceedings. Circuits, devices and systems. 2005, Vol 152, Num 3, pp 287-290, issn 1350-2409, 4 p.Article

All-analytic surface potential model for SOI MOSFETsYU, Y. S; KIM, S. H; HWANG, S. W et al.IEE proceedings. Circuits, devices and systems. 2005, Vol 152, Num 2, pp 183-188, issn 1350-2409, 6 p.Article

Approximate LMS tuning of continuous time filters : convergence and sensitivity analysisWESTWICK, D. T; MAUNDY, B; SALMEH, R et al.IEE proceedings. Circuits, devices and systems. 2005, Vol 152, Num 1, pp 1-6, issn 1350-2409, 6 p.Article

Decoupling technique for CMOS gate with strong-coupled componentsYANG, L; YUAN, J. S.IEE proceedings. Circuits, devices and systems. 2005, Vol 152, Num 3, pp 279-286, issn 1350-2409, 8 p.Article

Design of an area-efficient CMOS multiple-valued current comparator circuitKONG, Z.-H; YEO, K.-S; CHANG, C.-H et al.IEE proceedings. Circuits, devices and systems. 2005, Vol 152, Num 2, pp 151-158, issn 1350-2409, 8 p.Article

Fourth-order PLL loop filter design technique with invariant natural frequency and phase marginTHOMPSON, I. V; BRENNAN, P. V.IEE proceedings. Circuits, devices and systems. 2005, Vol 152, Num 2, pp 103-108, issn 1350-2409, 6 p.Article

Matched interconnect design using ground-surrounded microstrip lineKHALAJ-AMIRHOSSEINI, M; CHELDAVI, A.IEE proceedings. Circuits, devices and systems. 2005, Vol 152, Num 1, pp 71-75, issn 1350-2409, 5 p.Article

2-Terminal floating bandgap voltage referenceCHERRY, E. M.IEE proceedings. Circuits, devices and systems. 2005, Vol 152, Num 6, pp 729-734, issn 1350-2409, 6 p.Article

Digit-serial AB² systolic architecture in GF(2^m)KIM, N.-Y; YOO, K.-Y.IEE proceedings. Circuits, devices and systems. 2005, Vol 152, Num 6, pp 608-614, issn 1350-2409, 7 p.Article

Duty-cycle controller for low-jitter frequency-doubling DLLTAJALLI, A; ATARODI, M; BAZARGAN, H et al.IEE proceedings. Circuits, devices and systems. 2005, Vol 152, Num 5, pp 411-416, issn 1350-2409, 6 p.Article

Pixel-parallel digital CMOS implementation of image segmentation by region growingMORIMOTO, T; HARADA, Y; KOIDE, T et al.IEE proceedings. Circuits, devices and systems. 2005, Vol 152, Num 6, pp 579-589, issn 1350-2409, 11 p.Article

Programmable wide range voltage adder/subtractor and its application as an encoderMONPAPASSORN, A.IEE proceedings. Circuits, devices and systems. 2005, Vol 152, Num 6, pp 697-702, issn 1350-2409, 6 p.Article